Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 100

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
2. Write to the Timer High and Low Byte registers to set the starting count value. Writing
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. Write to the Timer Control Register to enable the timer.
7. Assert the Timer Input signal to initiate the counting.
CAPTURE/COMPARE Mode
In CAPTURE/COMPARE Mode, the timer begins counting on the first external Timer
Input transition. The acceptable transition (rising edge or falling edge) is set by the TPOL
bit in the Timer Control Register. The timer input is the system clock.
Every subsequent acceptable transition (after the first) of the Timer Input signal captures
the current count value. The Capture value is written to the Timer PWM High and Low
Byte registers. When the Capture event occurs, an interrupt is generated, the count value
in the Timer High and Low Byte registers is reset to
INPCAP
capture event.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001H
the timer interrupt is not because of an input capture event.
Observe the following steps for configuring a timer for CAPTURE/COMPARE Mode and
initiating the count:
1. Write to the Timer Control Register to:
–
–
these registers only affects the first pass in GATED Mode. After the first timer reset in
GATED Mode, counting always begins at the reset value of
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input deassertion and reload events. If appropriate, configure the timer interrupt to be
generated only at the input deassertion event or the reload event by setting TICONFIG
field of the TxCTL0 Register.
–
–
–
and counting resumes. The
Configure the timer for GATED Mode
Set the prescale value
Disable the timer
Configure the timer for CAPTURE/COMPARE Mode
Set the prescale value
bit in TxCTL0 Register is set to indicate the timer interrupt is caused by an input
P R E L I M I N A R Y
INPCAP
bit in TxCTL0 Register is cleared to indicate
0001H
Z8 Encore! XP
and counting resumes. The
0001H
Product Specification
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®
F082A Series
Operation
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