Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 179

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Bit
Field
RESET
R/W
Address
Bit
Field
RESET
R/W
Address
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
[7]
WDT_RES
[6]
WDT_AO
Flash Option Bit Address Space
Trim Bit Data Register
Flash Program Memory Address 0000H
WDT_RES WDT_AO
R/W
R/W
U
7
0
7
The Trim Bid Data (TRMDR) Register contains the read or write data for access to the
trim option bits (Table 87).
The first two bytes of Flash program memory at addresses
for the user-programmable Flash option bits.
Description
Watchdog Timer Reset
0 = Watchdog Timer time-out generates an interrupt request. Interrupts must be globally
1 = Watchdog Timer time-out causes a system reset. This setting is the default for unpro-
Watchdog Timer Always On
0 = Watchdog Timer is automatically enabled upon application of system power. Watch-
1 = Watchdog Timer is enabled upon execution of the WDT instruction. Once enabled,
Table 88. Flash Option Bits at Program Memory Address 0000H
enabled for the eZ8 CPU to acknowledge the interrupt request.
grammed (erased) Flash.
dog Timer can not be disabled.
the Watchdog Timer can only be disabled by a Reset or Stop Mode Recovery. This
setting is the default for unprogrammed (erased) Flash.
R/W
R/W
6
0
U
6
Table 87. Trim Bit Data Register (TRMDR)
R/W
R/W
OSC_SEL[1:0]
5
0
U
5
P R E L I M I N A R Y
Program Memory 0000H
TRMDR: Trim Bit Data
R/W
R/W
U
4
0
4
FF7H
VBO_AO
R/W
R/W
U
3
0
3
Z8 Encore! XP
Flash Option Bit Address Space
FRP
R/W
R/W
0000H
U
2
2
0
Product Specification
and
Reserved
R/W
R/W
0001H
U
1
0
1
®
F082A Series
are reserved
FWP
R/W
R/W
U
0
0
0
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