Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 45

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Z8F041APH020SG2156

Manufacturer Part Number
Z8F041APH020SG2156
Description
8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
Manufacturer
ZiLOG
Datasheet

Specifications of Z8F041APH020SG2156

Rohs
yes
Core
eZ8
Processor Series
Z8F041xx
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
4 KB
Data Ram Size
1 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
PDIP-20
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
8
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
PS022827-1212
Operating Mode
STOP Mode
Note:
Caution:
Stop Mode Recovery Using Watchdog Timer Time-Out
Stop Mode Recovery Using a GPIO Port Pin Transition
tor address. Following Stop Mode Recovery, the STOP bit in the Reset Status (RSTSTAT)
Register is set to 1. Table 10 lists the Stop Mode Recovery sources and resulting actions.
The text following provides more detailed information about each of the Stop Mode
Recovery sources.
If the Watchdog Timer times out during STOP Mode, the device undergoes a Stop Mode
Recovery sequence. In the Reset Status (RSTSTAT) Register, the WDT and STOP bits are
set to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and
the Z8 Encore! XP F082A Series device is configured to respond to interrupts, the eZ8
CPU services the Watchdog Timer interrupt request following the normal Stop Mode
Recovery sequence.
Each of the GPIO port pins may be configured as a Stop Mode Recovery input source. On
any GPIO pin enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery.
SMR pulses shorter than specified do not trigger a recovery (see
In this instance, the STOP bit in the Reset Status (RSTSTAT) Register is set to 1.
In STOP Mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input
Data registers record the Port transition only if the signal stays on the Port pin through
the end of the Stop Mode Recovery delay. As a result, short pulses on the Port pin can
initiate Stop Mode Recovery without being written to the Port Input Data Register or
Table 10. Stop Mode Recovery Sources and Resulting Action
Stop Mode Recovery Source
Watchdog Timer time-out when configured
for Reset
Watchdog Timer time-out when configured
for interrupt
Data transition on any GPIO port pin enabled
as a Stop Mode Recovery source
Assertion of external RESET Pin
Debug Pin driven Low
P R E L I M I N A R Y
System Reset
Action
Stop Mode Recovery
Stop Mode Recovery followed by
interrupt (if interrupts are enabled)
Stop Mode Recovery
System Reset
Z8 Encore! XP
Product Specification
Table 135
Stop Mode Recovery
®
F082A Series
on page 233).
28

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