Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 132

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
Bit
[2]
TDRE
[1]
TXE
[0]
CTS
Bit
Field
RESET
R/W
Address
Bit
[7:2]
[1]
NEWFRM
[0]
MPRX
UART Status 1 Register
UART Transmit Data Register
Description (Continued)
TDRE—Transmitter Data Register Empty
This bit indicates that the UART Transmit Data Register is empty and ready for additional data.
Writing to the UART Transmit Data Register resets this bit.
0 = Do not write to the UART Transmit Data Register.
1 = The UART Transmit Data Register is ready to receive an additional byte to be transmitted.
Transmitter Empty
This bit indicates that the Transmit Shift Register is empty and character transmission is finished.
0 = Data is currently transmitting.
1 = Transmission is complete.
CTS Signal
When this bit is read it returns the level of the CTS signal. This signal is active Low.
Description
Reserved
These bits are reserved and must be programmed to 000000.
New Frame
A status bit denoting the start of a new frame. Reading the UART Receive Data Register
resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
Multiprocessor Receive
Returns the value of the most recent multiprocessor bit received. Reading from the UART
Receive Data Register resets this bit to 0.
R
7
0
This register contains multiprocessor control and status bits.
Data bytes written to the UART Transmit Data (UxTXD) Register, shown in Table 67, are
shifted out on the TXDx pin. The Write-only UART Transmit Data Register shares a Reg-
ister File address with the read-only UART Receive Data Register.
R
6
0
Table 66. UART Status 1 Register (U0STAT1)
R
5
0
Reserved
P R E L I M I N A R Y
R
4
0
F44H
R/W
3
0
Z8 Encore! XP
UART Control Register Definitions
R/W
2
0
Product Specification
NEWFRM
R
1
0
®
F082A Series
MPRX
R
0
0
115