Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 200

• Manufacturer Part Number: Z8F041APH020SG2156
• Description: 8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
• Manufacturer: ZiLOG

Specifications of Z8F041APH020SG2156

• Rohs: yes
• Core: eZ8
• Processor Series: Z8F041xx
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: PDIP-20
• Mounting Style: Through Hole
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Interface Type: UART
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

PS022827-1212
START
Note:
OCD Data Format
OCD Auto-Baud Detector/Generator
•
Exiting DEBUG Mode
The device exits DEBUG Mode following any of these operations:
•
•
•
•
•
•
The OCD interface uses the asynchronous data format defined for RS-232. Each character
transmitted and received by the OCD consists of 1 Start bit, 8 data bits (least-significant
bit first) and 1 Stop bit as displayed in Figure 26.
When responding to a request for data, the OCD may commence transmitting immediately
after receiving the stop bit of an incoming frame. Therefore, when sending the stop bit, the
host must not actively drive the DBG pin High for more than 0.5 bit times. Zilog recom-
mends that, if possible, the host drives the DBG pin using an open drain output to avoid
this issue.
To run over a range of baud rates (data bits per second) with various system clock frequen-
cies, the On-Chip Debugger contains an Auto-Baud Detector/Generator. After a reset, the
OCD is idle until it receives data. The OCD requires that the first character sent from the
D0
DBG pin, the DBG feature is unlocked. After releasing PA2/RESET, it is pulled High.
At this point, the PA0/DBG pin may be used to autobaud and cause the device to enter
DEBUG Mode. See
page
Clearing the DBGMODE bit in the OCD Control Register to 0
Power-On Reset
Voltage Brown-Out reset
Watchdog Timer reset
Asserting the RESET pin Low to initiate a Reset
Driving the DBG pin Low while the device is in STOP Mode initiates a System Reset
If the PA2/RESET pin is held Low while a 32-bit key sequence is issued to the PA0/
185.
D1
D2
Figure 26. OCD Data Format
the OCD Unlock Sequence (8-Pin Devices Only) section on
P R E L I M I N A R Y
D3
D4
D5
Z8 Encore! XP
D6
Product Specification
D7
®
F082A Series
STOP
Operation
183