Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 51

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Z8F041APH020SG2156

Manufacturer Part Number
Z8F041APH020SG2156
Description
8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
Manufacturer
ZiLOG
Datasheet

Specifications of Z8F041APH020SG2156

Rohs
yes
Core
eZ8
Processor Series
Z8F041xx
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
4 KB
Data Ram Size
1 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
PDIP-20
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
8
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
PS022827-1212
Bit
Field
RESET
R/W
Address
Bit
[7]
LPO
[6:5]
[4]
VBO
[3]
TEMP
[2]
ADC
[1]
COMP
[0]
Note:
Description
Low-Power Operational Amplifier Disable
0 = LPO is enabled (this applies even in STOP Mode).
1 = LPO is disabled.
Reserved
These bits are reserved and must be programmed to 00.
Voltage Brown-Out Detector Disable
This bit and the VBO_AO Flash option bit must both enable the VBO for the VBO to be active.
0 = VBO enabled.
1 = VBO disabled.
Temperature Sensor Disable
0 = Temperature Sensor enabled.
1 = Temperature Sensor disabled.
Analog-to-Digital Converter Disable
0 = Analog-to-Digital Converter enabled.
1 = Analog-to-Digital Converter disabled.
Comparator Disable
0 = Comparator is enabled.
1 = Comparator is disabled.
Reserved
This bit is reserved and must be programmed to 0.
LPO
R/W
7
1
operational amplifier (LPO) is OFF. To use the LPO, clear the LPO bit, turning it ON.
Clearing this bit might interfere with normal ADC measurements on ANA0 (the LPO out-
put). This bit enables the amplifier even in STOP Mode. If the amplifier is not required in
STOP Mode, disable it. Failure to perform this results in STOP Mode currents greater than
specified.
This register is only reset during a POR sequence. Other system reset events do not affect it.
R/W
Table 13. Power Control Register 0 (PWRCTL0)
6
0
Reserved
R/W
5
0
P R E L I M I N A R Y
VBO
R/W
4
0
F80H
TEMP
R/W
3
0
Z8 Encore! XP
Power Control Register Definitions
ADC
R/W
2
0
Product Specification
COMP
R/W
1
0
®
F082A Series
Reserved
R/W
0
0
34

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