Z8F041APH020SG2156 ZiLOG, Z8F041APH020SG2156 Datasheet - Page 102

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Z8F041APH020SG2156

Manufacturer Part Number
Z8F041APH020SG2156
Description
8-bit Microcontrollers - MCU 4K FLASH 1K RAM 128B NVDS
Manufacturer
ZiLOG
Datasheet

Specifications of Z8F041APH020SG2156

Rohs
yes
Core
eZ8
Processor Series
Z8F041xx
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Program Memory Size
4 KB
Data Ram Size
1 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
PDIP-20
Mounting Style
Through Hole
A/d Bit Size
10 bit
A/d Channels Available
8
Interface Type
UART
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
17
Number Of Timers
2
Program Memory Type
Flash
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
PS022827-1212
Bit
Field
RESET
R/W
Address
Bit
[7]
TMODEHI
Timer Control Register Definitions
Timer 0–1 Control Registers
TMODEHI
Description
Timer Mode High Bit
This bit, along with the TMODE field in the TxCTL1 Register, determines the operating
mode of the timer. This bit is the most significant bit of the Timer mode selection value. See
the description of the
mode decoding.
R/W
7
0
The timer input can be used as a selectable counting source. It shares the same pin as the
complementary timer output. When selected by the GPIO Alternate Function registers,
this pin functions as a timer input in all modes except for the DUAL PWM OUTPUT
mode. For this mode, there is no timer input available.
This section defines the features of the following Timer Control registers.
Timer 0–1 Control
Timer 0–1 High and Low Byte
Timer Reload High and Low Byte
Timer 0–1 PWM High and Low Byte
The Timer Control registers are 8-bit read/write registers that control the operation of their
associated counter/timers.
Time 0–1 Control Register 0
The Timer Control Register 0 (TxCTL0) and Timer Control Register 1 (TxCTL1), shown
in Table 50, determine the timer operating mode. These registers each include a program-
mable PWM deadband delay, two bits to configure timer interrupt definition and a status
bit to identify if the most recent timer interrupt is caused by an input capture event.
R/W
Table 50. Timer 0–1 Control Register 0 (TxCTL0)
6
0
TICONFIG
Registers: see page 85
Timer 0–1 Control Register 1 (TxCTL1)
R/W
5
0
P R E L I M I N A R Y
Registers: see page 89
Reserved
R/W
Registers: see page 91
4
0
F06H, F0EH
Registers: see page 92
R/W
3
0
Z8 Encore! XP
Timer Control Register Definitions
PWMD
R/W
for details about the full timer
2
0
Product Specification
R/W
1
0
®
F082A Series
INPCAP
R
0
0
85

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