MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 960
MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Universal Serial Bus Interface
16-32
Offset 0x2_31A4
Reset
Reset
Bits
31
30
29
28
27
26
25
24
23
22
21
20
W
W
R
R
—
—
31
15
0
BSEIE
BSVIE
ASVIE
AVVIE
BSEIS
Name
1msE
1msS
DPIE
DPIS
IDIE
—
—
DPIE 1msE BSEIE BSVIE ASVIE AVVIE IDIE
DPS 1msT BSE
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
30
14
0
Reserved, should be cleared.
Data pulse interrupt enable
1 Enable
0 Disable
1-millisecond timer Interrupt enable
1 Enable
0 Disable
B session end interrupt enable
1 Enable
0 Disable
B session valid interrupt enable
1 Enable
0 Disable
A session valid interrupt enable
1 Enable
0 Disable
A VBus valid interrupt enable
1 Enable
0 Disable
USB ID interrupt enable.
1 Enable
0 Disable
Reserved, should be cleared.
Data pulse interrupt status. Set when data bus pulsing occurs on DP or DM. Data bus pulsing is only
detected when USBMODE[CM] = Host (11) and PORTSC[PP] (port power) = Off (0).
Software must write a one to clear this bit.
1-millisecond timer interrupt status. Set once every millisecond.
Software must write a one to clear this bit.
B session end interrupt status. Set when VBus has fallen below the B session end threshold.
Software must write a one to clear this bit.
29
13
0
28
12
0
Table 16-24. OTGSC Register Field Descriptions
Figure 16-21. OTG Status Control (OTGSC)
BSV
27
11
1
ASV
26
10
1
AVV
25
0
9
ID
24
0
8
All zeros
Description
—
23
0
7
DPIS 1msS BSEIS BSVIS ASVIS AVVIS IDIS
w1c
—
22
0
w1c
21
1
5
w1c
DP
20
0
4
w1c
OT
19
0
3
Freescale Semiconductor
w1c
—
18
0
2
Access: Mixed
w1c
VC
17
0
1
w1c
VD
16
0
0
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