MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 1126

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DUART
18.4
The communication channel provides a full-duplex asynchronous receiver and transmitter using an
operating frequency derived from the system clock signal.
The transmitter accepts parallel data with a write access to UTHR. In FIFO mode, the data is placed
directly into an internal transmitter shift register, or into the transmitter FIFO—see
Mode.”
START, STOP, and optional parity bits. Finally, the registers output a composite serial data stream on the
channel transmitter serial data output (SOUT). The transmitter status may be polled or interrupt driven.
The receiver accepts serial data on the channel receiver serial data input (SIN), converts the data into
parallel format, and checks for START, STOP, and parity bits. In FIFO mode, the receiver removes the
START, STOP, and parity bits and then transfers the assembled character from the receiver buffer, or
receiver FIFO. This transfer occurs in response to a read of the UART receiver buffer register (URBR).
The receiver status may be polled or interrupt-driven.
18-18
DMS
DMS
0
0
1
1
0
0
1
1
The transmitting registers convert the data to a serial bit stream by inserting the appropriate
FEN
FEN
Functional Description
0
1
0
1
0
1
0
1
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
DMA Mode
DMA Mode
0
0
0
1
0
0
0
1
RXRDY is set when there are no characters in the receiver FIFO or URBR.
RXRDY is set when the trigger level has not been reached and there has been no time out.
RXRDY is cleared when there is at least one character in the receiver FIFO or URBR.
RXRDY is cleared when the trigger level or a time-out has been reached. RXRDY remains
cleared until the receiver FIFO is empty.
Table 18-23. UDSR[RXRDY] Set Conditions
Table 18-24. UDSR[RXRDY] Cleared
Meaning
Meaning
Section 18.4.5, “FIFO
Freescale Semiconductor