MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 70
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table
Number
16-71
16-72
16-73
16-74
16-75
16-76
16-77
16-78
16-79
16-80
16-81
16-82
16-83
16-84
16-85
16-86
16-87
16-88
16-89
16-90
16-91
16-92
16-93
16-94
16-95
16-96
16-97
16-98
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
18-1
18-2
18-3
18-4
lxx
Summary siTD Split Transaction State............................................................................. 16-115
Example Case 2a—Software Scheduling siTDs for an IN Endpoint................................ 16-116
Summary of Transaction Errors ........................................................................................ 16-119
Summary Behavior on Host System Errors ...................................................................... 16-122
Endpoint Capabilities/Characteristics ............................................................................... 16-124
Current dTD Pointer.......................................................................................................... 16-125
Multiple Mode Control ..................................................................................................... 16-126
Next dTD Pointer .............................................................................................................. 16-126
dTD Token ........................................................................................................................ 16-127
Buffer Pointer Page 0 ........................................................................................................ 16-127
Buffer Pointer Page 1 ........................................................................................................ 16-128
Buffer Pointer Pages 2–4 .................................................................................................. 16-128
Device Controller State Information Bits ......................................................................... 16-130
Device Controller Endpoint Initialization......................................................................... 16-133
Device Controller Stall Response Matrix ......................................................................... 16-134
Variable Length Transfer Protocol Example (ZLT = 0) .................................................... 16-136
Variable Length Transfer Protocol Example (ZLT = 1) .................................................... 16-136
Interrupt/Bulk Endpoint Bus Response Matrix................................................................. 16-137
Control Endpoint Bus Response Matrix ........................................................................... 16-139
Isochronous Endpoint Bus Response Matrix .................................................................... 16-142
Device Error Matrix .......................................................................................................... 16-146
Error Descriptions ............................................................................................................. 16-147
Interrupt Handling Order .................................................................................................. 16-147
Low Frequency Interrupt Events....................................................................................... 16-148
Error Interrupt Events ....................................................................................................... 16-148
Functional Differences Between EHCI and EHCI with Embedded TT ........................... 16-149
Emulated Handshakes ....................................................................................................... 16-151
ULPI Timing ..................................................................................................................... 16-154
I
I
I
I2CnADR Field Descriptions................................................................................................ 17-5
I2Cn FDR Field Descriptions ............................................................................................... 17-6
I2CnCR Field Descriptions ................................................................................................... 17-7
I2CnSR Field Descriptions ................................................................................................... 17-8
I2CnDR Field Descriptions................................................................................................... 17-9
I2CnDFSRR Field Descriptions.......................................................................................... 17-10
DUART Signal Overview ..................................................................................................... 18-3
DUART Signals—Detailed Signal Descriptions .................................................................. 18-3
DUART Register Summary .................................................................................................. 18-4
URBR Field Descriptions ..................................................................................................... 18-6
2
2
2
C Interface Signal Descriptions ......................................................................................... 17-3
C Interface Signals—Detailed Signal Descriptions ........................................................... 17-4
C Memory Map .................................................................................................................. 17-4
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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