MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 950

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.3.2.10 Master Interface Data Burst Size Register (BURSTSIZE)—Non-EHCI
This register is not defined in the EHCI specification. This register is used to control and dynamically
change the burst size used during data movement on the initiator (master) interface.
16.3.2.11 Transmit FIFO Tuning Controls Register (TXFILLTUNING)—Non-EHCI
This register is not defined in the EHCI specification. This register is used to control and dynamically
change the burst size used during data movement on device DMA transfers. It is only used in host mode.
The fields in this register control performance tuning associated with how the USB DR module posts data
to the TX latency FIFO before moving the data onto the USB bus. The specific areas of performance
include the how much data to post into the FIFO and an estimate for how long that operation should take
in the target system.
Definitions:
T
T
T
T
T
16-22
Offset 0x2_3160
Reset 0
31–11
31–16
s
0
1
ff
p
10–0
15–8
Bits
Bits
7–0
= Total Packet Flight Time (send-only) packet (T
= Standard packet overhead
= Time to send data payload
= Total Packet Time (fetch and send) packet (T
= Time to fetch packet into TX FIFO up to specified level.
W
R
31
TXPBURST Programable TX burst length. This register represents the maximum length of a burst in 32-bit words
RXPBURST Programable RX burst length. This register represents the maximum length of a burst in 32-bit words
EPBASE
0
Name
Name
—
—
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
0
0
Reserved, should be cleared.
Reserved, should be cleared.
while moving data from system memory to the USB bus. Must not be set to greater that 16.
while moving data from the USB bus to system memory. Must not be set to greater than 16.
Endpoint list address. Address of the top of the endpoint list.
Table 16-18. ENDPOINTLISTADDR Register Field Descriptions
0
Figure 16-16. Master Interface Data Burst Size (BURSTSIZE)
0
Table 16-19. BURSTSIZE Register Field Descriptions
0
—
0
0
0
0
0
0
p
0
s
= T
= T
16 15
0
ff
0
0
+ T
Description
Description
+ T
0
s
)
1
)
0
TXPBURST
1
0
0
0
8
0
7
0
Freescale Semiconductor
0
RXPBURST
0
Access: Read/Write
1
0
0
0
0
0