MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 852

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
Table 15-136
15.6
15.6.1
This section describes how to connect the eTSEC to various interfaces: MII, RMII, RGMII, and RTBI. To
avoid confusion, all of the buses follow the bus conventions used in the IEEE 802.3 specification because
the PHYs follow the same conventions. (For instance, in the bus TSECn_TXD[3:0], bit 3 is the msb and
bit 0 is the lsb). If a mode does not use all input signals available to a particular eTSEC, those inputs that
are not used must be pulled low on the board.
15-134
12–15
Bits
4–6
8–9
10
11
0
1
2
3
7
Disable Rx Dis Disable receive disparity. This bit is cleared by default.
Disable Tx Dis Disable transmit disparity. This bit is cleared by default.
Clock Select Clock select. This bit is cleared by default.
Soft_Reset
AN Sense
Functional Description
MI Mode
Name
Connecting to Physical Interfaces on Ethernet
—
—
—
—
describes the fields of the TBICON register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Soft reset. This bit is cleared by default.
0 Normal operation.
1 Resets the functional modules in the TBI.
Reserved. (Ignore on read)
0 Normal operation.
1 Disables the running disparity calculation and checking in the receive direction.
0 Normal operation.
1 Disables the running disparity calculation and checking in the transmit direction.
Reserved
Auto-negotiation sense enable. This bit is cleared by default.
0 IEEE 802.3z Clause 37 behavior is desired, which results in the link not completing.
1 Allow the auto-negotiation function to sense either a Gigabit MAC in auto-negotiation bypass mode
Reserved
0 Allow the TBI to accept dual split-phase 62.5 MHz receive clocks.
1 Configure the TBI to accept a 125 MHz receive clock from the SerDes/PHY. The 125 MHz clock must
This bit describes the configuration mode of the TBI. The user reads a 1 while the TBI is configured in
GMII/MII mode (connected to a GMII/MII PHY) and a 0 while configured in TBI mode (connected to a
1000BASE-X SerDes). Its value is the inverse of ECNTRL[TBIM].
0 TBI mode.
1 GMII mode.
Reserved
or an older Gigabit MAC without auto-negotiation capability. If sensed, auto-negotiation complete
becomes true; however, the page received is low, indicating no page was exchanged. Management
can then act accordingly.
be physically connected to ‘PMA receive clock 0’ if using a parallel (non-SGMII) Ethernet protocol.
Table 15-136. TBICON Field Descriptions
Description
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