MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 1204
MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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I–I
Index-6
data transfer, 17-11
error handling
features, 17-2
frequency divider
functional description, 17-10
handshaking, 17-14
implementation details, 17-12
initialization/application information, 17-19–17-20
interrupts
memory map/register definition, 17-4
modes of operation, 17-2
overview, 1-16
register descriptions, 17-5–17-10
serial data/clock wires, 17-1
signals, 17-3–17-4
transaction protocol, 17-10
slave mode, 17-14
boot sequencer mode, 4-26, 17-16
frequency divider register (I2CFDR), 17-6
address compare, 17-13
control transfer, 17-12
transaction monitoring, 17-12
boot sequencer mode, see I
generation of SCL when SDA low, 17-22
initialization sequence, 17-21
post-transfer software response, 17-21
repeated START generation, 17-22
START generation, 17-11, 17-21
STOP generation, 17-12, 17-22
calling address match condition, 17-5
flowchart for interrupt service routine, 17-19
interrupt after transfer, 17-21
interrupt enable bit (I2CCR[MIEN]), 17-7
interrupt on START, 17-21
interrupt pending status bit (I2CSR[MIF]), 17-9
interrupt-driven byte-to-byte transfers, 17-2
read of last byte, 17-22
slave mode interrupt service routine guidelines, 17-22
boot sequencer mode, 17-2, 17-15
interrupt-driven byte-to-byte data transfer, 17-2
master mode, 17-2
slave mode, 17-2
by acronym, see Register Index
see also Signals, I
handshaking, 17-14
repeated START condition, 17-3, 17-12
slave address transmission, 17-11
START condition, 17-3, 17-11, 17-21
STOP condition, 17-3, 17-12, 17-22
for slave transmitter routine, 17-23
loss of arbitration, 17-23
mode
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
2
C
2
C interface, boot sequencer
IBATnU/L (instruction block address translation regs. 0–7,
ID register, 14-73
IEEE 1149.1 specifications
Initialization
Initialization/application information
Initiator write, 14-66
Instruction address translation, 7-18
Instruction cache enable, 7-21
Instruction cache flash invalidate, 7-22
Instruction cache lock, 7-22
Instruction cache way lock, 7-25
Instruction timing
int (internal interrupt signal), 8-2
INTA, 12-15
Integrated programmable interrupt controller, see IPIC
Interfaces
specification compliance, 20-3
DDR (initialization and application information), 9-49
eTSEC (initialization and application information),
I
CSB arbiter and bus monitor, 6-16
DMA/messaging unit, 12-20
GTM registers, 5-64
host controller, 16-68
I
LBC, 10-88
PCI, 13-60
power management control, 5-91
real time clock module
SPI, 19-16
watchdog timer, 5-35
overview, 7-35–7-36
see also Execution timing
I
JTAG
2
2
2
C interface (initialization and application information)
C interface, 17-19–17-20
C, 1-16
upper/lower), 7-3
programming different memory types, 9-50
see also eTSEC, configuration
STOP generation, 17-22
boot sequencer mode, see I
generation of SCL when SDA low, 17-22
initialization sequence, 17-21
post-transfer software response, 17-21
repeated START generation, 17-22
START generation, 17-11, 17-21
STOP generation, 17-12
RTC programming guidelines, 5-42
master programming example, 19-16
slave programming example, 19-16
block diagram, 20-1
15-143, 15-192
mode
2
C interface, boot sequencer
Freescale Semiconductor
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