MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 1149
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Chapter 20
JTAG/Testing Support
20.1
The device provides a JTAG (Joint Test Action Group) interface to facilitate boundary-scan testing. The
JTAG interface complies to the IEEE 1149.1 boundary-scan specification. For additional information
about JTAG operations, refer to the IEEE 1149.1 specification.
The JTAG interface consists of a set of five signals, three JTAG registers (see
Registers and Scan
A block diagram of the JTAG interface is shown in
20.2
The device provides the following five dedicated JTAG signals:
Freescale Semiconductor
•
•
•
Test data input (TDI)
Test data output (TDO)
Test mode select (TMS)
Overview
JTAG Signals
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
TRST
TMS
TDO
TCK
Chains,”) and a test access port (TAP) controller, described in the following sections.
TDI
Figure 20-1. JTAG Interface Block Diagram
Register
Bypass
Instruction
Decoder
Register
Boundary-Scan
Figure
Register
TAP Controller
20-1.
MUX
MPC8313E
MUX
Section 20.3, “JTAG
20-1
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