MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 477

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

10.3.1.12 Transfer Error Attributes Register (LTEATR)
The transfer error attributes register (LTEATR) captures source attributes of an error/event.
shows the LTEATR. After LTEATR[V] has been set, software must clear this bit to allow LTESR,
LTEATR, and LTEAR to update following any subsequent events/errors.
Freescale Semiconductor
Offset 0x0_50BC
Reset
10–11
13–29
Bits
6–7
12
30
31
5
8
9
W
R
0
WARA Write after read atomic (WARA) error interrupt enable.
RAWA Read after write atomic (RAWA) error interrupt enable.
Name
UCCI
—
WPI
CSI
CCI
—
—
—
2
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
RWB
Write protect error interrupt enable.
0 Write protect error reporting is disabled.
1 Write protect error reporting is enabled.
Reserved
0 WARA error reporting is disabled.
1 WARA error reporting is enabled.
0 RAWA error reporting is disabled.
1 RAWA error reporting is enabled.
Reserved
Chip select error interrupt enable.
0 Chip select error reporting is disabled.
1 Chip select error reporting is enabled.
Reserved
UPM Run pattern command completion Event interrupt enable.
0 UPM Run pattern command completion reporting is disabled.
1 UPM Run pattern command completion reporting is enabled.
FCM command completion Event interrupt enable.
0 Command completion reporting is disabled.
1 Command completion reporting is enabled.
3
4
Figure 10-16. Transfer Error Attributes Register (LTEATR
Table 10-18. LTEIR Field Descriptions (continued)
—
10 11
SRCID
All zeros
15 16
Description
PB
19 20
BNK
23 24
Enhanced Local Bus Controller
Access: Read/Write
—
Figure 10-16
30 31
10-29
V