MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 406
MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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DDR Memory Controller
Table 9-8
9.4.1.4
DDR SDRAM timing configuration register 0, shown in
between various SDRAM control commands.
9-12
Offset 0x100
Reset
13–15
16–31
Offset 0x104
Reset 0 0
0–12
Bits
W
R
W
R
0
RWT WRT RRT
0
EXT_REFREC
1
describes TIMING_CFG_3 fields.
Name
0 0 0
2
DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
—
3 4
Figure 9-4. DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)
Figure 9-5. DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
0
5
Reserved, should be cleared.
Extended refresh recovery time (t
until an activate command is allowed. This field is concatenated with TIMING_CFG_1[REFREC] to
obtain a 7-bit value for the total refresh recovery. Note that hardware adds an additional 8 clock
cycles to the final, 7-bit value of the refresh recovery. t
that t
000 0 clocks
001 16 clocks
010 32 clocks
011 48 clocks
100 64 clocks
101 80 clocks
110 96 clocks
111 112 clocks
Reserved, should be cleared.
WWT — ACT_PD_EXIT — PRE_PD_EXIT
—
0
6
0
7
RFC
Table 9-8. TIMING_CFG_3 Field Descriptions
8
0
is calculated as follows:
0
9
0
12 13
11
1
EXT_REFRE
12
0
C
RFC
13
0
All zeros
). Controls the number of clock cycles from a refresh command
15 16
0
Figure
Description
15
1
16
0 0 0 0
9-5, sets the number of clock cycles
—
RFC
19 20
= {EXT_REFREC || REFREC} + 8, such
ODT_PD_EXIT
0
0
—
0
23 24
1
Freescale Semiconductor
0 0 0 0 0 1 0 1
Access: Read/Write
Access: Read/Write
—
27 28
MRS_CYC
31
31
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