MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 1133
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Chapter 19
Serial Peripheral Interface
19.1
Overview
The serial peripheral interface (SPI) allows the device to exchange data between other PowerQUICC®
family chips, the MC68360, MC68302, M68HC11, and M68HC05 microcontroller families, and other
family devices. The SPI can be used to communicate with peripheral devices such as EEPROMs, real-time
clocks, A/D converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an
independent baud-rate generator, and a control unit. The transmitter and receiver sections use the same
clock, which is derived from the SPI baud rate generator in master mode or externally in slave mode.
During an SPI transfer, data is sent and received simultaneously.
The SPI receiver and transmitter are double-buffered, as shown in
Figure
19-1, giving an effective FIFO
size (latency) of 2 characters. The SPI’s MSB/LSB is shifted out first. When the SPI is disabled in the SPI
mode register (SPMODE[EN] = 0), it consumes little power.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Freescale Semiconductor
19-1
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