MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 58
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table
Number
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
8-20
8-21
8-22
lviii
ACR Field Descriptions .......................................................................................................... 6-3
ATR Field Descriptions........................................................................................................... 6-4
AER Field Descriptions .......................................................................................................... 6-5
AIDR Field Descriptions ........................................................................................................ 6-6
AMR Field Descriptions ......................................................................................................... 6-7
AEATR Field Descriptions ..................................................................................................... 6-8
AEADR Field Descriptions .................................................................................................... 6-9
AERR Field Descriptions...................................................................................................... 6-10
Address Only Transaction Type Encoding............................................................................ 6-14
Reserved Transaction Type Encoding................................................................................... 6-15
Illegal Transaction Type Encoding ....................................................................................... 6-15
MSR Bit Descriptions ........................................................................................................... 7-17
e300 HID0 Bit Descriptions.................................................................................................. 7-20
Using HID0[ECLK] and HID0[SBCLK] to Configure clk_out ........................................... 7-23
HID1 Bit Descriptions .......................................................................................................... 7-23
e300HID2 Bit Descriptions................................................................................................... 7-24
Interrupt Classifications ...................................................................................................... 7-31
Exceptions and Interrupts...................................................................................................... 7-32
Differences Between e300 and G2_LE Cores ...................................................................... 7-39
IPIC Signal Properties............................................................................................................. 8-5
IPIC External Signals—Detailed Signal Descriptions............................................................ 8-5
IPIC Register Address Map .................................................................................................... 8-6
SICFR Field Descriptions ....................................................................................................... 8-8
SIVCR Field Descriptions ...................................................................................................... 8-9
IVEC/CVEC/MVEC Field Definition ................................................................................... 8-9
SIPNR_H/SIFCR_H/SIMSR_H Bit Assignments................................................................ 8-11
SIPNR_H Field Descriptions ................................................................................................ 8-12
SIPNR_L/SIFCR_L/SIMSR_L Bit Assignments ................................................................. 8-12
SIPNR_L Field Descriptions ................................................................................................ 8-13
SIPRR_A Field Descriptions ................................................................................................ 8-14
SIPRR_D Field Descriptions ................................................................................................ 8-15
SIMSR_H Field Descriptions ............................................................................................... 8-16
SIMSR_L Field Descriptions................................................................................................ 8-16
SICNR Field Descriptions .................................................................................................... 8-17
SEPNR Field Descriptions.................................................................................................... 8-18
SMPRR_A Field Descriptions .............................................................................................. 8-19
SMPRR_B Field Descriptions .............................................................................................. 8-20
SEMSR Field Descriptions ................................................................................................... 8-21
SECNR Field Descriptions ................................................................................................... 8-22
SERSR/SERMR/SERFR Bit Assignments ........................................................................... 8-23
SERSR Field Descriptions .................................................................................................... 8-23
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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