MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 1121
MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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18.3.1.8
The UMCRs, shown in
UART bus.
Table 18-15
.
Freescale Semiconductor
Bits
0–2
4–5
3
6
7
Name
LOOP Local loopback mode
RTS
Offset: 0x0_4504, 0x0_4604
—
—
—
Reset
describes the UMCR fields.
MODEM Control Registers (UMCR1 and UMCR2)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
W
R
Table 18-14. Parity Selection Using ULCR[PEN], ULCR[SP], and ULCR[EPS]
Reserved, should be cleared
0 Normal operation.
1 Functionally, the data written to UTHR can be read from URBR of the same UART, and UMCR[RTS] is tied
Reserved
Ready to send
0 Negates corresponding UART_RTS output.
1 Assert corresponding UART_RTS output. Informs external MODEM or peripheral that the UART is ready
Reserved
to UMSR[CTS].
for sending/receiving data.
0
Figure 18-10. Modem Control Register (UMCR1 and UMCR2)
Figure
—
1
18-10, control the interface with the external peripheral device on the
Table 18-15. UMCR Field Descriptions
PEN
0
0
0
0
1
1
1
1
2
SP
0
0
1
1
0
0
1
1
LOOP
EPS
3
0
1
0
1
0
1
0
1
All zeros
Description
Parity Selected
Space parity
Even parity
Mark parity
Odd parity
No parity
No parity
No parity
No parity
4
—
5
Access: User read/write
RTS
6
—
7
DUART
18-13
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