MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 436
MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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DDR Memory Controller
9.5.4.1
9.5.5
The DDR memory controller transfers the mode register set commands to the SDRAM array, and it uses
the setting of TIMING_CFG_0[MRS_CYC] for the Mode Register Set cycle time.
Figure 9-27
code; the second corresponds to SDMODE. The Mode Register Set cycle time is set to 2 DRAM cycles.
9-42
•
•
•
If running with many devices, zero-delay PLL clock buffers, JEDEC-JESD82 standard, should be
used. These buffers were designed for DDR applications.
PCB traces for DDR clock signals should be short, all on the same layer, and of equal length and
loading.
DDR SDRAM manufacturers provide detailed information on PCB layout and termination issues.
DDR SDRAM Mode-Set Command Timing
SDRAM Clock
shows the timing of the mode-set command. The first transfer corresponds to the ESDMODE
MCK, MCK
Clock Distribution
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 9-26. DDR SDRAM Clock Distribution Example for x8 DDR SDRAMs
CS[0]
MDQ n
MRAS
MCAS
MDQS
MBA n
MWE
MCS
MA n
Figure 9-27. DDR SDRAM Mode-Set Command Timing
Code
0x4
0
1
DDR
Code
0x0
2
3
4
A[13:0], BA[2:0], MRAS, MCAS, MWE, CKE
DQ[0:7], DQS[0], DM[0]
DQ[8:15], DQS[1], DM[1]
DQ[16:23], DQS[2], DM[2]
DQ[24:31], DQS[3], DM[3]
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Freescale Semiconductor
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