MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 882
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Enhanced Three-Speed Ethernet Controllers
The contents of the Rx FCB are defined in
15-164
Bytes
0–1
0–1
12–13
8–11
Bits
14
15
0
1
2
3
4
5
6
7
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Name
GPFP
CTU
PER
VLN
TUP
ETU
CIP
EIP
IP6
IP
—
—
VLAN tag recognized. This bit is set only if RCTRL[VLEX] is set.
0 No VLAN tag recognized.
1 IEEE Std. 802.1Q VLAN tag found; VLAN control word in VLCTL is valid.
IP header found at layer 3.RCTRL[PRSDEP] must be set to 10 or 11 in order to enable IP
discovery. See also IP6 bit of FCB.
0 No layer 3 header recognized.
1 An IP header was recognized at layer 3; the IANA protocol identifier for the next header can be
If S/W is relying on the RxFCB for the parse results, any RxFCB[IP] bits set with the corresponding
RxFCB[PRO] = 0xFF indicates a fragmented packet (or that this packet had a back-to-back IPv6
routing extension header). Additionally, RQFPR[IPF] (see
Filer Table Property Register
IP version 6 header found at layer 3.
0 No IPv6 header was found.
1 The layer 3 header was an IPv6 header provided IP = 1.
TCP or UDP header found at layer 4. RCTRL[PRSDEP] must be set to 10 or 11 in order to enable
TCP/UDP discovery.
0 No layer 4 header recognized.
1 The layer 4 header was recognized as either TCP (PRO = 0x06) or UDP (PRO = 0x11).
IPv4 header checksum checked. RCTRL[PRSDEP] must be set to 10 or 11 in order to enable IPv4
checksum verification.
0 IPv4 header checksum not verified, either because verification was disabled or a valid IPv4
1 IPv4 header checksum was verified by the eTSEC, and bit EIP indicates result.
TCP or UDP header checksum checked. RCTRL[PRSDEP] must be set to 11 in order to enable
layer 4 checksum verification.
0 TCP or UDP header checksum not verified, either because verification was disabled or a valid
1 TCP or UDP header checksum was verified by the eTSEC, and ETU indicates result.
IPv4 header checksum verification error. Not valid unless CIP = 1.
0 No checksum error in IPv4 header.
1 Error in header checksum only if IP = 1 and IP6 = 0.
TCP or UDP header checksum verification error. Not valid unless CTU = 1.
0 No checksum error in TCP or UDP header.
1 Error in header checksum only if PRO = 0x06 or PRO = 0x11.
Reserved
Parse error.
00 No error in L2 to L4 parse
01 Reserved
10 Inconsistent or unsupported L3 header sequence
11 Reserved
Reserved
General-purpose filer event packet. This packet was filed based on matching a GPI rule sequence.
found in PRO; see PRO for more information.
header could not be located.
TCP or UDP header could not be located. If a UDP header with zero checksum was located,
this bit is cleared in accordance with RFC 768.
Table 15-153. Rx Frame Control Block Descriptions
Table
(RQFPR)”) indicates that the packet was fragmented.
15-153.
Description
Section 15.5.3.3.8, “Receive Queue
Freescale Semiconductor
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