MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 696

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
The channel will wait indefinitely for the controller to complete a requested activity before continuing to
the next step of descriptor processing.
The channel can generate two types of done notification signals when it completes operation on a
descriptor—an interrupt and/or a writeback of the descriptor header. The done interrupt is enabled by the
CDIE bit and the done writeback is enabled by the CDWE bit of the channel configuration register
(Table
status writeback can also be used to signal processing completion. Any descriptor can have status
writeback occur as a result of the AWSE bit of the channel configuration register. Or, by setting IWSE,
status writeback will occur when any ICV-checking descriptor completes.
The selected done notification can be performed at the end of processing of every descriptor, or only on
selected descriptors. If the NT field is 0 in the channel configuration register, then done notification is
performed after every descriptor. If the NT field is 1, done notification is only performed on descriptors in
which the DN bit is set in the packet header
14-54
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14-31).
Transfer data parcels (up to 32 Kbytes) from system memory into assigned EU input registers and
FIFOs. This may involve using link tables to gather input data that has been split into multiple
segments which are stored in various locations of system memory. For the RAID-XOR descriptor
type, the channel rotates among three data sources, fetching 32 bytes from each source.
Transfer data parcels (up to 32 Kbytes) from assigned EU output registers and FIFOs to system
memory space. This may involve using link tables to scatter output data into multiple segments
which are stored in various locations of system memory.
Initialize the end-of-message register (where applicable) in the assigned EU upon completion of
last EU write indicated by the descriptor. The channel will wait for a indication from the EU that
processing of input text-data is complete before proceeding with further activity after writing
end-of-message.
Reset assigned EU(s).
Release assigned EU(s).
When a descriptor has been completely processed, provide feedback to the host, in the form of
interrupt and/or descriptor header write-back to system memory.
When descriptor processing is halted due to an error, provide feedback to the host through an
interrupt.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 14-5
shows the DONE field that is written back in if writeback is enabled. In addition,
(Table
14-4).
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