MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 395
MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Chapter 9
DDR Memory Controller
9.1
The fully programmable DDR SDRAM controller supports most JEDEC standard x8, x16, or x32 DDR2
and DDR memories available. In addition, unbuffered and registered DRAM modules are supported.
However, mixing different memory types or unbuffered and registered DRAM modules in the same system
is not supported. Dynamic power management and auto-precharge modes simplify memory system design.
A large set of special features support rapid system debug.
Freescale Semiconductor
Introduction
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
In this chapter, the word ‘bank’ refers to a physical bank specified by a chip
select; ‘logical bank’ refers to one of the four or eight sub-banks in each
SDRAM chip. A sub-bank is specified by the 2 or 3 bits on the bank address
(MBA) pins during a memory access.
NOTE
9-1
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