MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 69
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table
Number
16-30
16-31
16-32
16-33
16-34
16-35
16-36
16-37
16-38
16-39
16-40
16-41
16-42
16-43
16-44
16-45
16-46
16-47
16-48
16-49
16-50
16-51
16-52
16-53
16-54
16-55
16-56
16-57
16-58
16-59
16-60
16-61
16-62
16-63
16-64
16-65
16-66
16-67
16-68
16-69
16-70
Freescale Semiconductor
ENDPTCOMPLETE Register Field Descriptions .............................................................. 16-37
ENDPTCTRL0 Register Field Descriptions ....................................................................... 16-38
ENDPTCTRLn Register Field Descriptions ....................................................................... 16-39
SNOOPn Register Field Descriptions................................................................................. 16-41
AGE_CNT_THRESH Register Field Descriptions ............................................................ 16-42
PRI_CTRL Register Field Descriptions ............................................................................. 16-43
SI_CTRL Register Field Descriptions ................................................................................ 16-43
CONTROL Field Descriptions ........................................................................................... 16-44
Supported PHY Interfaces .................................................................................................. 16-46
Typ Field Encodings ........................................................................................................... 16-49
Next Schedule Element Pointer .......................................................................................... 16-50
iTD Transaction Status and Control.................................................................................... 16-51
Buffer Pointer Page 0 (Plus) ............................................................................................... 16-52
iTD Buffer Pointer Page 1 (Plus) ........................................................................................ 16-52
Buffer Pointer Page 2 (Plus) ............................................................................................... 16-52
Buffer Pointer Page 3–6 ...................................................................................................... 16-52
Next Link Pointer................................................................................................................ 16-53
Endpoint and Transaction Translator Characteristics ......................................................... 16-54
Micro-Frame Schedule Control .......................................................................................... 16-54
siTD Transfer Status and Control........................................................................................ 16-54
siTD Buffer Pointer Page 0 (Plus) ...................................................................................... 16-55
siTD Buffer Pointer Page 1 (Plus) ...................................................................................... 16-56
siTD Back Link Pointer ...................................................................................................... 16-56
qTD Next Element Transfer Pointer (DWord 0) ................................................................. 16-57
qTD Alternate Next Element Transfer Pointer (DWord 1) ................................................. 16-57
qTD Token (DWord 2) ........................................................................................................ 16-58
qTD Buffer Pointer ............................................................................................................. 16-61
Queue Head DWord 0 ......................................................................................................... 16-62
Endpoint Characteristics: Queue Head DWord 1................................................................ 16-63
Endpoint Capabilities: Queue Head DWord 2 .................................................................... 16-64
Current qTD Link Pointer ................................................................................................... 16-65
Host-Controller Rules for Bits in Overlay (DWords 5, 6, 8, and 9) ................................... 16-66
FTSN Normal Path Pointer ................................................................................................. 16-67
FSTN Back Path Link Pointer ............................................................................................ 16-67
Behavior During Wake-Up Events...................................................................................... 16-71
Operation of FRINDEX and SOFV (SOF Value Register)................................................. 16-75
Example Periodic Reference Patterns for Interrupt Transfers ............................................ 16-88
Ping Control State Transition Table .................................................................................... 16-89
Interrupt IN/OUT Do Complete Split State Execution Criteria........................................ 16-103
Initial Conditions for OUT siTD TP and T-Count Fields ..................................................16-111
Transaction Position (TP)/Transaction Count (T-Count) Transition Table........................16-111
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Tables
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Tables
Number
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