MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 769
MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table 15-28
Freescale Semiconductor
16–23
Bits
0–7
10
11
12
13
14
15
24
8
9
QHLT0 RxBD queue 0 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
QHLT1 RxBD queue 1 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
QHLT2 RxBD queue 2 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
QHLT3 RxBD queue 3 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
QHLT4 RxBD queue 4 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
QHLT5 RxBD queue 5 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
QHLT6 RxBD queue 6 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
QHLT7 RxBD queue 7 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
Name
RXF0 Receive frame event occurred on ring 0. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
—
—
describes the fields of the RSTAT register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
not cause a QHLT0 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
not cause a QHLT1 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
not cause a QHLT2 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
not cause a QHLT3 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
not cause a QHLT4 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
not cause a QHLT5 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
not cause a QHLT6 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
not cause a QHLT7 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
Reserved
frame to this ring.
Table 15-28. RSTAT Field Descriptions
Description
Enhanced Three-Speed Ethernet Controllers
15-51
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