S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 642

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
The MSCAN facilitates a sophisticated message storage system which addresses the requirements of a
broad range of network applications.
16.4.2.1
Modern application layer software is built upon two fundamental assumptions:
The behavior described in the bullets above cannot be achieved with a single transmit buffer. That buffer
must be reloaded immediately after the previous message is sent. This loading process lasts a finite amount
of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted
stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts
with short latencies to the transmit interrupt.
A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending
and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a
message is finished while the CPU re-loads the second buffer. No buffer would then be ready for
transmission, and the CAN bus would be released.
At least three transmit buffers are required to meet the first of the above requirements under all
circumstances. The MSCAN has three transmit buffers.
The second requirement calls for some sort of internal prioritization which the MSCAN implements with
the “local priority” concept described in
16.4.2.2
The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple
messages to be set up in advance. The three buffers are arranged as shown in
All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see
Section 16.3.3, “Programmer’s Model of Message
Register (TBPR) contains an 8-bit local priority field (PRIO) (see
Priority Register
(see
To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set
transmitter buffer empty (TXEx) flag (see
(CANTFLG)”). If a transmit buffer is available, the CPU must set a pointer to this buffer by writing to the
CANTBSEL register (see
(CANTBSEL)”). This makes the respective buffer accessible within the CANTXFG address space (see
Section 16.3.3, “Programmer’s Model of Message
CANTBSEL register simplifies the transmit buffer selection. In addition, this scheme makes the handler
642
•
•
Section 16.3.3.5, “Time Stamp Register
Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus
between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the
previous message and only release the CAN bus in case of lost arbitration.
The internal message queue within any CAN node is organized such that the highest priority
message is sent out first, if more than one message is ready to be sent.
Message Transmit Background
Transmit Structures
(TBPR)”). The remaining two bytes are used for time stamping of a message, if required
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register
MC9S12XE-Family Reference Manual Rev. 1.25
Section 16.4.2.2, “Transmit
Section 16.3.2.7, “MSCAN Transmitter Flag Register
(TSRH–TSRL)”).
Storage”). The algorithmic feature associated with the
Storage”). An additional Transmit Buffer Priority
Section 16.3.3.4, “Transmit Buffer
Structures.”
Figure
Freescale Semiconductor
16-39.