S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 111

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
2.3.8
2.3.9
Freescale Semiconductor
Function
Address 0x0005 (PRR)
Address 0x0006 (PRR)
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Altern.
Field
Reset
Reset
7-0
PD
W
W
R
R
Port D general purpose input/output data—Data Register
Port D pins 7 through 0 are associated with data I/O lines DATA[7:0] respectively in expanded modes.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
DDRC7
DATA7
Port D Data Register (PORTD)
Port C Data Direction Register (DDRC)
PD7
0
0
7
7
DDRC6
DATA6
PD6
0
0
6
6
Figure 2-7. Port C Data Direction Register (DDRC)
Table 2-9. PORTD Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 2-6. Port D Data Register (PORTD)
DDRC5
DATA5
PD5
0
0
5
5
DDRC4
DATA4
PD4
0
0
4
4
Description
DDRC3
DATA3
PD3
3
0
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
DDRC2
DATA2
PD2
0
0
2
2
Access: User read/write
Access: User read/write
DDRC1
DATA1
PD1
0
0
1
1
DDRC0
DATA0
PD0
0
0
0
0
111
(1)
(1)