S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 233

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

4.3.1.4
Read: Anytime
Write: Never
4.3.1.5
Read: Anytime
Write: Anytime
Freescale Semiconductor
Address: Module Base + 0x0003
Address: Module Base + 0x0005
ADDR[7:0]
SEL[2:0]
Reset
Reset
SVSEN
Field
Field
7–0
2–0
7
W
W
R
R
SVSEN
MPU Address Status Register 2 (MPUASTAT2)
MPU Descriptor Select Register (MPUSEL)
Access violation address bits — The ADDR[7:0] bits contain bits [7:0] of the global address which caused
the current access violation interrupt. These bits are undefined if the access error flag bit (AEF) in the MPUFLG
register is not set.
MPU supervisor state enable bit — This bit enables the memory protection for the CPU in supervisor state.
If this bit is cleared, the MPU does not affect any accesses coming from the CPU in supervisor state. This is to
prevent the CPU from locking out itself while configuring the protection descriptors (during initialization after a
system reset and during the update of the protection descriptors for a task switch). The memory protection
functionality for the other bus-masters is unaffected by this bit.
0 MPU is disabled for the CPU in supervisor state
1 MPU is enabled for the CPU in supervisor state
Descriptor select bits — The SEL[2:0] bits select which descriptor is visible in the MPU Descriptor Register
window (MPUDESC0—MPUDESC5).
0
0
7
7
Figure 4-6. MPU Address Status Register (MPUASTAT2)
0
0
0
Figure 4-7. MPU Descriptor Select Register (MPUSEL)
6
6
MC9S12XE-Family Reference Manual Rev. 1.25
Table 4-6. MPUASTAT2 Field Descriptions
Table 4-7. MPUSEL Field Descriptions
0
0
0
5
5
0
0
0
4
4
ADDR[7:0]
Description
Description
0
0
0
3
3
Chapter 4 Memory Protection Unit (S12XMPUV1)
0
0
2
2
SEL[2:0]
0
0
1
1
0
0
0
0
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