S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 527
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S912XET512J3VALR
Manufacturer Part Number
S912XET512J3VALR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XET512J3VALR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12XE
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
32 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XET512J3VALR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 14
Enhanced Capture Timer (ECT16B8CV3)
14.1
The HCS12 enhanced capture timer module has the features of the HCS12 standard timer module
enhanced by additional features in order to enlarge the field of applications, in particular for automotive
ABS applications.
This design specification describes the standard timer as well as the additional features.
The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. This timer can
be used for many purposes, including input waveform measurements while simultaneously generating an
output waveform. Pulse widths can vary from microseconds to many seconds.
A full access for the counter registers or the input capture/output compare registers will take place in one
clock cycle. Accessing high byte and low byte separately for all of these registers will not yield the same
result as accessing them in one word.
14.1.1
Freescale Semiconductor
Revision
Number
V03.06
V03.07
V03.08
•
16-bit buffer register for four input capture (IC) channels.
Introduction
Revision Date
Features
04 May 2010
05 Aug 2009
26 Aug 2009
14.3.2.2/14-536
14.3.2.3/14-536
14.3.2.4/14-537
14.3.2.8/14-540
14.4.1.1.2/14-
14.3.2.15/14-
14.3.2.16/14-
14.3.2.24/14-
14.3.2.29/14-
14.3.2.11/14-
Sections
Affected
549
551
557
562
573
543
MC9S12XE-Family Reference Manual Rev. 1.25
Table 14-1. Revision History
update register PACTL bit4 PEDGE PT7 to IC7
update register PAFLG bit0 PAIF PT7 to IC7,update bit1 PAOVF PT3 to IC3
update register ICSYS bit3 TFMOD PTx to ICx
update register PBFLG bit1 PBOVF PT1 to IC1
update IC Queue Mode description.
- Add description, ?a counter overflow when TTOV[7] is set?, to be the
condition of channel 7 override event.
- Phrase the description of OC7M to make it more explicit
- Add
- TCRE description, add Note and
Table 14-11
Description of Changes
Figure 14-17
527
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