S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 218

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

Chapter 3 Memory Mapping Control (S12XMMCV4)
3.4.4.1
The arbitration scheme allows only one master to be connected to a target at any given time. The following
rules apply when prioritizing accesses from different masters to the same target bus:
3.5
3.5.1
CALL and RTC instructions are uninterruptable CPU instructions that automate page switching in the
program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is
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CPU always has priority over BDM and XGATE.
XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU
for its duration.
XGATE has priority over BDM.
BDM has priority over CPU and XGATE when its access is stalled for more than 128 cycles. In the
later case the suspect master will be stalled after finishing the current operation and the BDM will
gain access to the bus.
In emulation modes all internal accesses are visible on the external bus as well and the external bus
is used during access to the PRU registers.
EBI
Initialization/Application Information
XGATE
CALL and RTC Instructions
XBUS3
Master Bus Prioritization regarding access conflicts on Target Buses
XGATE
XBUS1
FLASH
DBG
FTM
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 3-23. MMC Block Diagram
MMC “Crossbar Switch”
EEE
XBUS0
CPU
S12X0
resources
BDM
BDM
S12X1
XSRAM
XRAM
Freescale Semiconductor
FLEXRAY
IPBI
S12X2
XBUS2