S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 1224
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S912XET512J3VALR
Manufacturer Part Number
S912XET512J3VALR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XET512J3VALR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12XE
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
32 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XET512J3VALR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Appendix A Electrical Characteristics
A.3
A.3.1
The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency f
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. When attempting to program or erase the NVM
modules at a lower frequency, a full program or erase transition is not assured.
The program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV
register. The frequency of this clock must be set within the limits specified as f
The minimum program and erase times shown in
maximum f
A.3.1.1
The time it takes to perform a blank check is dependant on the location of the first non-blank word starting
at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the command. Assuming
that no non blank location is found, then the erase verify all blocks is given by.
A.3.1.2
The time it takes to perform a blank check is dependant on the location of the first non-blank word starting
at relative address zero. It takes one bus cycle per phrase to verify plus a setup of the command. Assuming
that no non blank location is found, then the erase verify time for a single 256K NVM array is given by
For a 128K NVM or D-Flash array the erase verify time is given by
A.3.1.3
The maximum time depends on the number of phrases being verified (N
1224
t
t
t
t
check
check
check
check
=
=
=
=
NVM, Flash and Emulated EEPROM
NVMBUS
Timing Parameters
33500
33500
17200
(
752
Erase Verify All Blocks (Blank Check) (FCMD=0x01)
Erase Verify Block (Blank Check) (FCMD=0x02)
Erase Verify P-Flash Section (FCMD=0x03)
+
⋅
⋅
⋅
N
unless otherwise shown. The maximum times are calculated for minimum f
--------------------- -
f
--------------------- -
f
--------------------- -
f
NVMOSC
NVMBUS
NVMBUS
NVMBUS
VP
)
1
1
1
⋅
--------------------- -
f
NVMBUS
is required for performing program or erase operations. The NVM modules
1
MC9S12XE-Family Reference Manual Rev. 1.25
Table A-19
are calculated for maximum f
VP
)
NVMOP
Freescale Semiconductor
.
NVMOP
NVMOP
and
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