S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 286

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S912XET512J3VALR

Manufacturer Part Number
S912XET512J3VALR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XET512J3VALR

Rohs
yes
Core
HCS12X
Processor Series
MC9S12XE
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
32 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S912XET512J3VALR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 7 Background Debug Module (S12XBDMV2)
7.3.2.2
Register Global Address 0x7FFF06
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte
of the condition code register of the user’s program. It is also used for temporary storage in the standard
BDM firmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.
7.3.2.3
Register Global Address 0x7FFF07
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR HIGH holding register is used to save the high
byte of the condition code register of the user’s program. The BDM CCR HIGH holding register can be
written to modify the CCR value.
286
Special Single-Chip Mode
Reset
W
R
All Other Modes
BDM CCR LOW Holding Register (BDMCCRL)
BDM CCR HIGH Holding Register (BDMCCRH)
0
0
7
When BDM is made active, the CPU stores the content of its CCR
in the BDMCCRL register. However, out of special single-chip reset, the
BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the
CCR
BDMCCRL register is read zero.
Reset
L
W
= Unimplemented or Reserved
R
register in this CPU mode. Out of reset in all other modes the
Figure 7-5. BDM CCR HIGH Holding Register (BDMCCRH)
Figure 7-4. BDM CCR LOW Holding Register (BDMCCRL)
CCR7
0
0
6
1
0
7
MC9S12XE-Family Reference Manual Rev. 1.25
CCR6
1
0
6
5
0
0
CCR5
0
0
5
NOTE
0
0
4
CCR4
0
0
4
0
0
3
CCR3
1
0
3
CCR10
2
0
CCR2
0
0
2
L
register
Freescale Semiconductor
CCR9
0
1
CCR1
0
0
1
CCR8
CCR0
0
0
0
0
0

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