S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 137
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S912XET512J3VALR
Manufacturer Part Number
S912XET512J3VALR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XET512J3VALR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12XE
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
32 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XET512J3VALR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1. Read: Anytime.
2.3.45
Freescale Semiconductor
Function
Address 0x0258
Write: Anytime.
Altern.
Field
Reset
PTP
PTP
PTP
PTP
7
6
5
4
W
R
Port P general purpose input/output data—Data Register
Port P pin 6 is associated with the PWM output channel 7 and the SCK signal of SPI2.
The PWM function takes precedence over the SPI2 and the general purpose I/O function if the PWM channel 7 is
enabled. The SPI2 function takes precedence of the general purpose I/O function if the routed SPI2 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Port P general purpose input/output data—Data Register
Port P pin 6 is associated with the PWM output channel 6 and the SS signal of SPI2.
The PWM function takes precedence over the SPI2 and the general purpose I/O function if the PWM channel 6 is
enabled. The SPI2 function takes precedence of the general purpose I/O function if the routed SPI2 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Port P general purpose input/output data—Data Register
Port P pin 5 is associated with the PWM output channel 5 and the MOSI signal of SPI2.
The PWM function takes precedence over the SPI2 and the general purpose I/O function if the PWM channel 5 is
enabled. The SPI2 function takes precedence of the general purpose I/O function if the routed SPI2 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Port P general purpose input/output data—Data Register
Port P pin 4 is associated with the PWM output channel 4 and the MISO signal of SPI2.
The PWM function takes precedence over the SPI2 and the general purpose I/O function if the PWM channel 4 is
enabled. The SPI2 function takes precedence of the general purpose I/O function if the routed SPI2 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
PWM7
PTP7
SCK2
Port P Data Register (PTP)
0
7
PWM6
PTP6
SS2
0
6
Table 2-41. PTP Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 2-43. Port P Data Register (PTP)
PWM5
MOSI2
PTP5
0
5
MISO2
PWM4
PTP4
0
4
Description
PWM3
PTP3
SS1
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
PWM2
SCK1
PTP2
0
2
Access: User read/write
MOSI1
PWM1
PTP1
0
1
MISO1
PWM0
PTP0
0
0
137
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