S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 387

• Manufacturer Part Number: S912XET512J3VALR
• Description: 16-bit Microcontrollers - MCU 16 BIT,512K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S912XET512J3VALR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12XE
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-112
• Mounting Style: SMD/SMT

10.8.2.5
This addressing mode is used to identify the position and size of a bit field for insertion or extraction. The
width and offset are coded in the lower byte of the source register 2, RS2. The content of the upper byte is
ignored. An offset of 0 denotes the right most position and a width of 0 denotes 1 bit. These instructions
are very useful to extract, insert, clear, set or toggle portions of a 16 bit word
10.8.2.6
The XGATE offers a number of additional instructions for flag manipulation, program flow control and
debugging:
10.8.3
Table 10-23
letter implies additional wait cycles if memories or peripherals are not accessible. Memories or peripherals
are not accessible if they are blocked by the S12X_CPU. In addition to this Peripherals are only accessible
every other XGATE cycle. Uppercase letters denote 16 bit operations. Lowercase letters denote 8 bit
operations. The XGATE is able to perform two bus or wait cycles per S12X_CPU cycle.
Freescale Semiconductor
1. SIF: Set a channel interrupt flag
2. SSEM: Test and set a hardware semaphore
3. CSEM: Clear a hardware semaphore
4. BRK: Software breakpoint
5. NOP: No Operation
6. RTS: Terminate the current thread
BFEXT
Cycle Notation
show the XGATE access detail notation. Each code letter equals one XGATE cycle. Each
Bit Field Operations
Special Instructions for DMA Usage
15
15
R3,R4,R5 ; R5: W4+1 bits with offset O4, will be extracted from R4 into R3
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 10-26. Bit Field Addressing
Bit Field Insert
7
W4
W4=3, O4=2
5
4
3
3
2
O4
Bit Field Extract
0
0
0
RS2
RS1
RD
Chapter 10 XGATE (S12XGATEV3)
387