S912XET512J3VALR Freescale Semiconductor, S912XET512J3VALR Datasheet - Page 1000

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S912XET512J3VALR

Manufacturer Part Number
S912XET512J3VALR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XET512J3VALR

Rohs
yes
Core
HCS12X
Processor Series
MC9S12XE
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
32 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-112
Mounting Style
SMD/SMT

Available stocks

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Part Number
Manufacturer
Quantity
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Part Number:
S912XET512J3VALR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1)
26.4.2.13 Set User Margin Level Command
The Set User Margin Level command causes the Memory Controller to set the margin level for future read
operations of a specific P-Flash or D-Flash block.
Upon clearing CCIF to launch the Set User Margin Level command, the Memory Controller will set the
user margin level for the targeted block and then set the CCIF flag.
Valid margin level settings for the Set User Margin Level command are defined in
1000
FERSTAT
Register
FSTAT
CCOBIX[2:0]
Table 26-57. Set User Margin Level Command FCCOB Requirements
Table 26-56. Verify Backdoor Access Key Command Error Handling
000
001
MGSTAT1
MGSTAT0
EPVIOLIF
ACCERR
Error Bit
FPVIOL
1. Read margin to the erased state
2. Read margin to the programmed state
(CCOBIX=001)
Table 26-58. Valid Set User Margin Level Settings
0x0000
0x0001
0x0002
CCOB
MC9S12XE-Family Reference Manual Rev. 1.25
Set if CCOBIX[2:0] != 100 at command launch
Set if a Load Data Field command sequence is currently active
Set if an incorrect backdoor key is supplied
Set if backdoor key access has not been enabled (KEYEN[1:0] != 10, see
Section
Set if the backdoor key has mismatched since the last reset
None
None
None
None
0x0D
26.3.2.2)
Return to Normal Level
User Margin-1 Level
User Margin-0 Level
FCCOB Parameters
Margin level setting
Level Description
Global address [22:16] to identify the
Error Condition
(1)
(2)
Flash block
Table
Freescale Semiconductor
26-58.

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