AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 84

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Abort Status
Embedded Flash
Controller
Misalignment
Detector
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AT91SAM7S32 Preliminary
There are three reasons for an abort to occur:
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When an abort occurs, a signal is sent back to all the masters, regardless of which one has
generated the access. However, only the ARM7TDMI can take an abort signal into account,
and only under the condition that it was generating an access. The Peripheral Data Controller
does not handle the abort input signal. Note that the connection is not represented in Figure
28.
To facilitate debug or for fault analysis by an operating system, the Memory Controller inte-
grates an Abort Status register set.
The full 32-bit wide abort address is saved in MC_AASR. Parameters of the access are saved
in MC_ASR and include:
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In the case of a Data Abort from the processor, the address of the data access is stored. This
is useful, as searching for which address generated the abort would require disassembling the
instructions and full knowledge of the processor context.
In the case of a Prefetch Abort, the address may have changed, as the prefetch abort is pipe-
lined in the ARM processor. The ARM processor takes the prefetch abort into account only if
the read instruction is executed and it is probable that several aborts have occurred during this
time. Thus, in this case, it is preferable to use the content of the Abort Link register of the ARM
processor.
The Embedded Flash Controller is added to the Memory Controller and ensures the interface
of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode for
Code Fetch with its system of 32-bit buffers. It also manages with the programming, erasing,
locking and unlocking sequences thanks to a full set of commands.
The Memory Controller features a Misalignment Detector that checks the consistency of the
accesses.
For each access, regardless of the master, the size of the access and the bits 0 and 1 of the
address bus are checked. If the type of access is a word (32-bit) and the bits 0 and 1 are not 0,
or if the type of the access is a half-word (16-bit) and the bit 0 is not 0, an abort is returned to
the master and the access is cancelled. Note that the accesses of the ARM processor when it
is fetching instructions are not checked.
The misalignments are generally due to software bugs leading to wrong pointer handling.
These bugs are particularly difficult to detect in the debug phase.
As the requested address is saved in the Abort Status Register and the address of the instruc-
tion generating the misalignment is saved in the Abort Link Register of the processor,
detection and fix of this kind of software bug is simplified.
access to an undefined address
an access to a misaligned address.
the size of the request (field ABTSZ)
the type of the access, whether it is a data read or write, or a code fetch (field ABTTYP)
whether the access is due to accessing an undefined address (bit UNDADD) or a
misaligned address (bit MISADD)
the source of the access leading to the last abort (bits MST0 and MST1)
whether or not an abort occurred for each master since the last read of the register (bit
SVMST0 and SVMST1) unless this information is loaded in MST bits
6071A–ATARM–28-Oct-04