AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 132

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Interrupt Latencies
External Interrupt
Edge Triggered
Source
External Interrupt
Level Sensitive Source
132
AT91SAM7S32 Preliminary
Global interrupt latencies depend on several parameters, including:
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This section addresses only the hardware resynchronizations. It gives details of the latency
times between the event on an external interrupt leading in a valid interrupt (edge or level) or
the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the
processor. The resynchronization time depends on the programming of the interrupt source
and on its type (internal or external). For the standard interrupt, resynchronization times are
given assuming there is no higher priority in progress.
The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt
sources.
Figure 48. External Interrupt Edge Triggered Source
Figure 49. External Interrupt Level Sensitive Source
The time the software masks the interrupts.
Occurrence, either at the processor level or at the AIC level.
The execution time of the instruction in progress when the interrupt occurs.
The treatment of higher priority interrupts and the resynchronization of the hardware
signals.
(Negative Edge)
(Positive Edge)
IRQ or FIQ
IRQ or FIQ
nIRQ
MCK
nFIQ
(High Level)
(Low Level)
IRQ or FIQ
IRQ or FIQ
MCK
nIRQ
nFIQ
Maximum IRQ Latency = 4 Cycles
Maximum FIQ Latency = 4 Cycles
Latency = 3 Cycles
Latency = 3 cycles
Maximum IRQ
Maximum FIQ
6071A–ATARM–28-Oct-04