AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 354

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Timer/Counter (TC) User Interface
Global Register Mapping
Table 76. Timer/Counter (TC) Global Register Map
Channel Memory Mapping
Table 77. Timer/Counter (TC) Channel Memory Mapping
Note:
354
Offset
Offset
0x30-0xFC
0xC0
0xC4
0x00
0x40
0x80
0x0C
0x1C
0x2C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
1. Read only if WAVE = 0
AT91SAM7S32 Preliminary
Channel/Register
TC Channel 0
TC Channel 1
TC Channel 2
TC Block Control Register
TC Block Mode Register
Register
Channel Control Register
Channel Mode Register
Reserved
Reserved
Counter Value
Register A
Register B
Register C
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Reserved
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the whole TC
block. TC channels are controlled by the registers listed in
channel registers in
tioned in
Table 77
.
Table 77
is in relation to the offset of the corresponding channel as men-
TC_CMR
TC_CCR
TC_IMR
TC_IDR
TC_IER
TC_RC
TC_CV
TC_RA
TC_RB
TC_SR
Name
TC_BMR
TC_BCR
Name
–
–
–
Read/Write
Read/Write
Read/Write
Read/Write
See Table 77
See Table 77
See Table 77
Write-only
Read-only
Read-only
Write-only
Write-only
Read-only
Read/Write
Access
Write-only
Access
–
–
–
Table 77
(1)
(1)
. The offset of each of the
6071A–ATARM–28-Oct-04
Reset Value
Reset Value
–
0
–
–
0
0
0
0
0
–
–
0
–
–
0