AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 371

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Functional
Description
PWM Clock
Generator
6071A–ATARM–28-Oct-04
The PWM macrocell is primarily composed of a clock generator module and 4 channels.
Figure 162. Functional View of the Clock Generator Block Diagram
Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock
in the Power Management Controller (PMC).
The PWM macrocell master clock, MCK, is divided in the clock generator module to provide
different clocks available for all channels. Each channel can independently select one of the
divided clocks.
The clock generator is divided in three blocks:
Each linear divider can independently divide one of the clocks of the modulo n counter. The
selection of the clock to be divided is made according to the PREA (PREB) field of the PWM
–
–
–
–
–
Clocked by the system clock, MCK, the clock generator module provides 13
clocks.
Each channel can independently choose one of the clock generator outputs.
Each channel generates an output waveform with attributes that can be defined
independently for each channel through the user interface registers.
a modulo n counter which provides 11 clocks: F
F
two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and
clkB
MCK
/16, F
MCK
/32, F
MCK
MCK
/64, F
modulo n counter
MCK
/128, F
AT91SAM7S32 Preliminary
PREA
PREB
PWM_MR
PWM_MR
MCK
Divider A
Divider B
/256, F
DIVA
DIVB
MCK
MCK
MCK/2
MCK/4
MCK/8
MCK/16
MCK/32
MCK/64
MCK/128
MCK/256
MCK/512
MCK/1024
MCK
, F
MCK
/512, F
clkA
clkB
/2, F
MCK
MCK
/1024
/4, F
MCK
/8,
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