AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 42

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Functional
Description
NRST Manager
NRST Signal or Interrupt
NRST External Reset
Control
42
AT91SAM7S32 Preliminary
The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup
Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset
signals:
•
•
•
These reset signals are asserted by the Reset Controller, either on external events or on soft-
ware action. The Reset State Manager controls the generation of reset signals and provides a
signal to the NRST Manager when an assertion of the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling
external device resets.
The NRST Manager samples the NRST input pin and drives this pin low when required by the
Reset State Manager. Figure 14 shows the block diagram of the NRST Manager.
Figure 14. NRST Manager
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected
low, a User Reset is reported to the Reset State Manager.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of
NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in
RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit
clears only when RSTC_SR is read.
The Reset Controller can also be programmed to generate an interrupt instead of generating a
reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1.
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this
occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the
field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH,
lasts 2
between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the
NRST pulse.
proc_nreset: Processor reset line. It also resets the Watchdog Timer.
periph_nreset: Affects the whole set of embedded peripherals.
nrst_out: Drives the NRST pin.
(ERSTL+1)
NRST
Slow Clock cycles. This gives the approximate duration of an assertion
RSTC_SR
nrst_out
URSTS
NRSTL
External Reset Timer
RSTC_MR
RSTC_MR
ERSTL
URSTEN
RSTC_MR
URSTIEN
interrupt
sources
Other
user_reset
exter_nreset
6071A–ATARM–28-Oct-04
rstc_irq