AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 373

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

6071A–ATARM–28-Oct-04
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Figure 164. Non Overlapped Center Aligned Waveforms
Note:
When center aligned, the internal channel counter increases up to CPRD and .decreases
down to 0. This ends the period.
When left aligned, the internal channel counter increases up to CPRD and is reset. This ends
the period.
Thus, for the same CPRD value, the period for a center aligned channel is twice the period for
a left aligned channel.
Waveforms are fixed at 0 when:
•
•
PWM0
PWM1
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula
will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula
becomes, respectively:
the waveform duty cycle . This channel parameter is defined in the CDTY field of the
PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
the waveform polarity. At the beginning of the period, the signal can be at high or low
level. This property is defined in the CPOL field of the PWM_CMRx register. By default the
signal starts by a low level.
the waveform alignment . The output waveform can be left or center aligned. Center
aligned waveforms can be used to generate non overlapped waveforms. This property is
defined in the CALG field of the PWM_CMRx register. The default mode is left aligned.
CDTY = CPRD and CPOL = 0
CDTY = 0 and CPOL = 1
---------------------------------------- -
--------------------------------------------------- -
duty cycle
duty cycle
2
2
1. See Figure 165 on page 375 for a detailed description of center aligned waveforms.
X
CPRD
MCK
MCK
CPRD
=
=
No overlap
DIVA
------------------------------------------------------------------------------------------------------- -
---------------------------------------------------------------------------------------------------------------------- -
period 1 fchannel_x_clock
period 2
or
Period
–
--------------------------------------------------- -
2
CPRD
–
1 fchannel_x_clock
MCK
period
period 2
DIVB
AT91SAM7S32 Preliminary
CDTY
CDTY
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