AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 202

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Synchronous Data
Output
Multi Drive Control
(Open Drain)
Output Line
Timings
Figure 77. Output Line Timings
Inputs
202
Write PIO_ODSR at 1
Write PIO_ODSR at 0
Write PIO_SODR
Write PIO_CODR
AT91SAM7S32 Preliminary
PIO_ODSR
PIO_PDSR
MCK
the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is con-
figured to be controlled by the PIO controller or assigned to a peripheral function. This enables
configuration of the I/O line prior to setting it to be managed by the PIO Controller.
Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it
defines the first level driven on the I/O line.
Controlling all parallel busses using several PIOs requires two successive write operations in
the PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The
PIO controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Out-
put Data Status Register). Only bits unmasked by PIO_OSWSR (Output Write Status
Register) are written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Out-
put Write Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable
Register).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets
at 0x0.
Each I/O can be independently programmed in Open Drain by using the Multi Drive feature.
This feature permits several drivers to be connected on the I/O line which is driven low only by
each device. An external pull-up resistor (or enabling of the internal one) is generally required
to guarantee a high level on the line.
The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and
PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O
line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-
driver Status Register) indicates the pins that are configured to support external drivers.
After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.
Figure 77 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by
directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR
is set. Figure 77 also shows when the feedback in PIO_PDSR is available.
The level on each I/O line can be read through PIO_PDSR (Peripheral Data Status Register).
This register indicates the level of the I/O lines regardless of their configuration, whether
uniquely as an input or driven by the PIO controller or driven by a peripheral.
APB Access
2 cycles
APB Access
2 cycles
6071A–ATARM–28-Oct-04