AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 237
AT91SAM7S32-AI
Manufacturer Part Number
AT91SAM7S32-AI
Description
AT91 ARM Thumb-based Microcontrollers
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT91SAM7S32-AI.pdf
(446 pages)
- Current page: 237 of 446
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SPI Mode Register
Name:
Access Type:
• MSTR: Master/Slave Mode
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
• PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
• PCSDEC: Chip Select Decode
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder. The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules:
• FDIV: Clock Selection
0 = The SPI operates at MCK.
1 = The SPI operates at MCK/N.
• MODFDIS: Mode Fault Detection
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
• LLB: Local Loopback Enable
0 = Local loopback path disabled.
1 = Local loopback path enabled.
LLB controls the local loopback on the data serializer for testing in Master Mode only.
6071A–ATARM–28-Oct-04
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 15.
LLB
31
23
15
–
–
7
SPI_MR
Read/Write
30
22
14
–
–
6
–
29
21
13
–
–
–
5
MODFDIS
28
20
12
–
–
4
DLYBCS
FDIV
27
19
11
–
3
AT91SAM7S32 Preliminary
PCSDEC
26
18
10
–
2
PCS
PS
25
17
–
1
9
MSTR
24
16
8
–
0
237
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