AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 389
AT91SAM7S32-AI
Manufacturer Part Number
AT91SAM7S32-AI
Description
AT91 ARM Thumb-based Microcontrollers
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT91SAM7S32-AI.pdf
(446 pages)
- Current page: 389 of 446
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Analog-to-digital Converter (ADC)
Overview
Block Diagram
6071A–ATARM–28-Oct-04
The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital
Converter (ADC). It also integrates an 8-to-1 analog multiplexer, making possible the analog-
to-digital conversions of up to eight analog lines. The conversions extend from 0V to ADVREF.
The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a
common register for all channels, as well as in a channel-dedicated register. Software trigger,
external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter out-
put(s) are configurable.
The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC
channel. These features reduce both power consumption and processor intervention.
Finally, the user can configure ADC timings, such as Startup Time and Sample & Hold Time.
Figure 168. Analog-to-Digital Converter Block Diagram
ADVREF
ADTRG
VDDIN
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
PIO
Selection
Channels
Trigger
Counter
Timer
Analog-to-Digital
Approximation
Successive
Converter
Register
ADC
AT91SAM7S32 Preliminary
Interface
Control
Logic
User
ADC Interrupt
PDC
AIC
Peripheral Bridge
ASB
APB
389
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