AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 231

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Clock Generation
Transfer Delays
Figure 86. Programmable Delays
Peripheral Selection
6071A–ATARM–28-Oct-04
Chip Select 1
Chip Select 2
SPCK
The SPI Baud rate clock is generated by dividing the Master Clock (MCK) or the Master Clock
divided by 32, by a value between 2 and 255. The selection between Master Clock or Master
Clock divided by N is done by the FDIV value set in the Mode Register
This allows a maximum operating baud rate at up to Master Clock/2 and a minimum operating
baud rate of MCK divided by 255*32.
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can
lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first
transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in
the SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the
baud rate for each interfaced peripheral without reprogramming.
Figure 86 shows a chip select transfer change and consecutive transfers on the same chip
select. Three delays can be programmed to modify the transfer waveforms:
•
•
•
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and
bus release time.
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By
default, all the NPCS signals are high before and after each transfer.
The peripheral selection can be performed in two different ways:
•
•
The delay between chip selects, programmable only once for all the chip selects by writing
the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one
chip select and before assertion of a new one.
The delay before SPCK, independently programmable for each chip select by writing the
field DLYBS. Allows the start of SPCK to be delayed after the chip select has been
asserted.
The delay between consecutive transfers, independently programmable for each chip
select by writing the DLYBCT field. Allows insertion of a delay between two transfers
occurring on the same chip select
Fixed Peripheral Select: SPI exchanges data with only one peripheral
Variable Peripheral Select: Data can be exchanged with more than one peripheral
DLYBCS
DLYBS
AT91SAM7S32 Preliminary
DLYBCT
DLYBCT
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