AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 383

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AT91SAM7S32-AI

Manufacturer Part Number
AT91SAM7S32-AI
Description
AT91 ARM Thumb-based Microcontrollers
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
PWM Interrupt Mask Register
Register Name: PWM_IMR
Access Type:
• CHIDx: Channel ID.
0 = Interrupt for PWM channel x is disabled.
1 = Interrupt for PWM channel x is enabled.
PWM Interrupt Status Register
Register Name: PWM_ISR
Access Type:
• CHIDx: Channel ID
0 = No new channel period has been achieved since the last read of the PWM_ISR register.
1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
Note: Reading PWM_ISR automatically clears CHIDx flags.
6071A–ATARM–28-Oct-04
31
23
15
31
23
15
7
7
Read-only
Read-only
30
22
14
30
22
14
6
6
29
21
13
29
21
13
5
5
28
20
12
28
20
12
4
4
CHID3
CHID3
27
19
27
19
11
11
3
3
AT91SAM7S32 Preliminary
CHID2
CHID2
26
18
10
26
18
10
2
2
CHID1
CHID1
25
17
25
17
9
1
9
1
CHID0
CHID0
24
16
24
16
8
0
8
0
383

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