AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 391

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Functional Description
Analog-to-digital
Conversion
Conversion
Reference
Conversion
Resolution
Conversion
Results
6071A–ATARM–28-Oct-04
The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a
10-bit digital data requires Sample and Hold Clock cycles as defined in the field SHTIM of the
“ADC Mode Register” on page 397 and 10 ADC Clock cycles. The ADC Clock frequency is
selected in the PRESCAL field of the Mode Register (ADC_MR).
The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set
to 63 (0x3F). PRESCAL must be programmed in order to provide an ADC clock frequency
according to the parameters given in the Product definition section.
The conversion is performed on a full range between 0V and the reference voltage pin
ADVREF. Analog inputs between these voltages convert to values based on a linear
conversion.
The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit
LOWRES in the ADC Mode Register (ADC_MR). By default, after a reset, the resolution is the
highest and the DATA field in the data registers is fully used. By setting the bit LOWRES, the
ADC switches in the lowest resolution and the conversion results can be read in the eight low-
est significant bits of the data registers. The two highest bits of the DATA field in the
corresponding ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0.
Moreover, when a PDC channel is connected to the ADC, 10-bit resolution sets the transfer
request sizes to 16-bit. Setting the bit LOWRES automatically switches to 8-bit data transfers.
In this case, the destination buffers are optimized.
When a conversion is completed, the resulting 10-bit digital value is stored in the Channel
Data Register (ADC_CDR) of the current channel and in the ADC Last Converted Data Regis-
ter (ADC_LCDR).
The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case
of a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either
EOC and DRDY can trigger an interrupt.
Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading
ADC_LCDR clears the DRDY bit and the EOC bit corresponding to the last converted channel.
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