AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 372

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

PWM Channel
Block Diagram
Waveform Properties
372
AT91SAM7S32 Preliminary
Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by
DIVA (DIVB) field value in the PWM Mode register (PWM_MR).
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode regis-
ter are set to 0. This implies that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This sit-
uation is also true when the PWM master clock is turned off through the Power Management
Controller.
Figure 163. Functional View of the Channel Block Diagram
Each of the 4 channels is composed of three blocks:
•
•
•
The different properties of output waveforms are:
•
•
clock generator
Inputs from
Inputs from
A clock selector which selects one of the clocks provided by the clock generator described
in Section “PWM Clock Generator” on page 371.
An internal counter clocked by the output of the clock selector. This internal counter is
incremented or decremented according to the channel configuration and comparators
events. The size of the internal counter is 16 bits.
A comparator used to generate events according to the internal counter value. It also
computes the PWMx output waveform according to the configuration.
the internal clock selection . The internal channel counter is clocked by one of the clocks
provided by the clock generator described in the previous section. This channel parameter
is defined in the CPRE field of the PWM_CMRx register. This field is reset at 0.
the waveform period . This channel parameter is defined in the CPRD field of the
PWM_CPRDx register.
- If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be claculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula
will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula
becomes, respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
------------------------------ -
----------------------------------------- -
X
CRPD
APB Bus
MCK
CPRD
MCK
DIVA
Channel
Selector
Clock
or
--------------------------------------------- -
CRPD
MCK
DIVAB
Counter
Internal
Comparator
6071A–ATARM–28-Oct-04
PWMx
output waveform