AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 394

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Sleep Mode and
Conversion
Sequencer
ADC Timings
394
AT91SAM7S32 Preliminary
If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the
selected signal. If one of the TIOA outputs is selected, the corresponding Timer Counter chan-
nel must be programmed in Waveform Mode.
Only one start command is necessary to initiate a conversion sequence on all the channels.
The ADC hardware logic automatically performs the conversions on the active channels, then
waits for a new request. The Channel Enable (ADC_CHER) and Channe l Disab le
(ADC_CHDR) Registers enable the analog channels to be enabled or disabled independently.
If the ADC is used with a PDC, only the transfers of converted data from enabled channels are
performed and the resulting data buffers should be interpreted accordingly.
Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus,
if a hardware trigger is selected, the start of a conversion can be initiated either by the hard-
ware or the software trigger.
The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it
is not being used for conversions. Sleep Mode is selected by setting the bit SLEEP in the
Mode Register ADC_MR.
The SLEEP mode is automatically managed by a conversion sequencer, which can automati-
cally process the conversions of all channels at lowest power consumption.
When a start conversion request occurs, the ADC is automatically activated. As the analog cell
requires a start-up time, the logic waits during this time and starts the conversion on the
enabled channels. When all conversions are complete, the ADC is deactivated until the next
trigger. Triggers occurring during the sequence are not taken into account.
The conversion sequencer allows automatic processing with minimum processor intervention
and optimized power consumption. Conversion sequences can be performed periodically
using a Timer/Counter output. The periodic acquisition of several samples can be processed
automatically without any intervention of the processor thanks to the PDC.
Note:
Each ADC has its own minimal Startup Time that is programmed through the field STARTUP
in the Mode Register ADC_MR.
In the same way, a minimal Sample and Hold Time is necessary for the ADC to guarantee the
best converted final value between two channels selection. This time has to be programmed
through the bitfield SHTIM in the Mode Register ADC_MR.
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be
taken into consideration to program a precise value in the SHTIM field. See the section DC
Characteristics in the product datasheet.
The reference voltage pins always remain connected in normal mode as in sleep mode.
6071A–ATARM–28-Oct-04