XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 93

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

In-System Programming Support
usually preprogrammed before it is mounted on the printed
circuit board. In-system programming support is available
from third-party boundary-scan tool vendors and from some
third-party PROM programmers using a socket adapter with
attached wires. To gain access to the parallel Flash signals,
drive the FPGA’s PROG_B input Low with an open-drain
driver. This action places all FPGA I/O pins, including those
attached to the parallel Flash, in high-impedance (Hi-Z). If
the HSWAP input is Low, the I/Os have pull-up resistors to
the V
programming hardware then has direct access to the paral-
lel Flash pins. The programming access points are high-
lighted in the gray boxes in
The FPGA itself can also be used as a parallel Flash PROM
programmer during development and test phases. Initially,
an FPGA-based programmer is downloaded into the FPGA
via JTAG. Then the FPGA performs the Flash PROM pro-
gramming algorithms and receives programming data from
the host via the FPGA’s JTAG interface. See Chapter 11 in
Embedded System Tools Reference
DS312-2 (v3.4) November 9, 2006
Product Specification
I
Recommend
open-drain
PROG_B
In a production application, the parallel Flash PROM is
driver
CCO
TMS
TCK
TDO
TDI
JTAG
2.5V
input on their respective I/O bank. The external
R
Not available
in VQ100
package
BPI Mode
‘0’
‘1’
A
‘0’
‘0’
P
HSWAP
M2
M1
M0
CSI_B
RDWR_B
TDI
TMS
TCK
PROG_B
Figure 58
Spartan-3E
FPGA
VCCINT
+1.2V
GND
VCCAUX
VCCO_0
VCCO_1
VCCO_2
A[23:17]
Figure 59: Daisy-Chaining from BPI Flash Mode
CSO_B
A[16:0]
INIT_B
DONE
Manual.
BUSY
D[7:0]
CCLK
LDC0
LDC1
LDC2
HDC
and
TDO
Figure
VCCO_0
+2.5V
V
V
59.
www.xilinx.com
I
+2.5V
CE#
OE#
WE#
BYTE#
DQ[15:7]
DQ[7:0]
A[n:0]
VCC
GND
Dynamically Loading Multiple Configuration
Images Using MultiBoot Option
After the FPGA configures itself using BPI mode from one
end of the parallel Flash PROM, then the FPGA can trigger
a MultiBoot event and reconfigure itself from the opposite
end of the parallel Flash PROM. MultiBoot is only available
when using BPI mode and only for applications with a single
Spartan-3E FPGA.
By default, MultiBoot mode is disabled. To trigger a Multi-
Boot event, assert a Low pulse lasting at least 300 ns on the
MultiBoot
STARTUP_SPARTAN3E
signal returns High after the 300 ns or longer pulse, the
FPGA automatically reconfigures from the opposite end of
the parallel Flash memory.
Figure 60
loads itself from the attached parallel Flash PROM. In this
example, the M0 mode pin is Low so the FPGA starts at
address 0 and increments through the Flash PROM mem-
ory locations. After the FPGA completes configuration, the
application initially loaded into the FPGA performs a
board-level or system test using FPGA logic. If the test is
V
x8/x16
PROM
Flash
x8 or
D
V
shows an example usage. At power up, the FPGA
Parallel
Slave
Mode
‘1’
‘1’
‘0’
‘0’
P
Trigger
HSWAP
M2
M1
M0
CCLK
CSI_B
RDWR_B
TDI
TMS
TCK
PROG_B
Spartan-3E
FPGA
VCCINT
library primitive. When the MBT
+1.2V
GND
(MBT)
VCCAUX
VCCO_0
VCCO_1
VCCO_2
CSO_B
INIT_B
DONE
BUSY
D[7:0]
TDO
Functional Description
input
VCCO_0
VCCO_1
+2.5V
V
DS312-2_50_103105
to
CCLK
D[7:0]
CSO_B
PROG_B
TCK
TMS
DONE
INIT_B
the
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